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      SOC芯片设计系列培训之DFT & Digital IC Testing
   入学要求

        学员学习本课程应具备下列基础知识:
        ◆ 电路系统的基本概念。

   班级规模及环境
       为了保证培训效果,增加互动环节,我们坚持小班授课,每期报名人数限3到5人,多余人员安排到下一期进行。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦
近开课时间(周末班/连续班/晚班)
DFT培训班:2018年6月11日
   学时
     ◆课时: 共5天,30学时

        ◆外地学员:代理安排食宿(需提前预定)
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        ☆边讲边练

        ☆合格学员免费推荐工作

        

        专注高端培训17年,曙海提供的课程得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

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   新优惠
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          SOC芯片设计系列培训之DFT & Digital IC Testing
  • Outlines

    Testing Components: That’s All You Have To Do In Testing

    Briefly speaking, they consist of internal tests, which are normally DFT oriented, functional tests, parametric tests and environment tests. This section is going to talk about what they are and how they impact your testing life.

    ATE & IC Testing: Too Expensive to Ignore It

    What cause ATEs expensive are the precision, speed, memory, channels and integration of digital and analog test functionalities. What do the ATE specs mean to you? Topics include waveforms, strobes, PMU, cost estimation, breakeven point calculation, etc. How they associate with IC testing. Availability and specifications of ATEs limit your design flow, test strategy and time-to-market.

    Trend in ATE: structural tester, low cost tester. What they do and how they reduce your cost.

    Traditional Testing: More Challenges And Expensive

    Event driven and cycle based tests. How people develop the functional patterns for digital IC: verilog testbench to VCD. Advantages and disadvantages of functional tests. ATEs and functional tests. What are parametric tests? Open/short tests. IDD Test. Output voltage testing. Input leakage testing, Tristate leakage test. Wafer sorting. Testing Pies (overlap of different type of patterns detecting faults).

    Test Economics: My Managers’ Jobs
    Moore’s cycle. Test preparation (DFT logics, test-related silicon., pattern generation, pattern simulation, and tester program generation). Test execution (DUT card design, probe cards, temperature generator, handler, drier, production test time, IC debugging, ATE cost). Test escape cost. Defect level (Yield loss vs Test coverage). Diagnosis, Failure analysis. Cost of failure at different stages. Time-to-market, time-to-yield.

    Test cycle (test time) calculation.
    Test economics drives DFT technology, low cost DFT oriented tester and standard test program.

    DFT Technology

     

    --Scan and Faults: Cornerstone Of DFT technology
    Common scan types. Scan variations. How scan work? Scan in ATPG. Scan in BIST. Scan in Boundary scan. DC scan, AC scan (LOS, LOC). How defects are modeled? Fault types.

    --Test Synthesis: Key To High Test Coverage And Design Penalty
    Scan insertion. Partial scan, full scan. Scan assembly, chain balance, lockup latch placement. Dealing with the multiple phase clocks. Bottom up and top down test synthesis. How to deal with multiple types of scan cells. Test Synthesis rules.

    -- DRC rules: The Bridges To Success
    Clock rules, bus (bidi) rules, AVI rules, data traction rules, memory test rules, scan tracing rules.

    --ATPG and Pattern generation: Let Machine Do It??
    ATPG algorithm. Procedures. True beauty of fault simulation. How to fault simulation functional patterns in ATPG? Bus contention in pattern generation. Abort limit. Sequential ATPG.

    Pre-shift, post-shift, end-measurement. Strobe edges: where do I put them (give out an example)
    Fault collapsing. Why ATPG untestable, why DI, UU, TI, BL, RE etc. What’s the atpg? effectiveness? What’s the test coverage and fault coverage? How do you calculate the test coverage? How to increase the test coverage? On chip PLL testing (new method in ac scan). Z masking, padding. Scan cell mask, outputs mask in transition faults.

    --BIST: Pros And Cons
    Memory faults. Memory testing methods. Embedded memory testing, at-speed memory testing. Logic BIST structural, the benefits and the penalty. LBIST flow: phase shift, PRPG, MISR, x-bounding. At-speed logic BIST. ATPG top-up in logic BIST design.

    --Boundary Scan: Don’t Think It’s Too Simple
    Structure of Boundary scan. Can control Memory BIST, LBIST, ATPG (state machine analysis plus an example). Can do board testing (JTAG technology, Asset International). An example on atpg through boundary scan.

    --Pattern Optimization and Technology: Great Area to Hammer DFT
    Pattern compression during ATPG. Pattern ordering. EDT technology, DBIST, XDBIST (deterministic BIST). Macro pattern, fault simulation. Transition pattern generation to iddq pattern generation.

     

    --Diagnosis: Did I Really Do Something Wrong?
    Scan logs. How many failed patterns you need to do diagnosis? What does the values mean in fault simulation and good simulation values. Memory BIST diagnosis. LBIST diagnosis: the difficult thing. How to correlate the pattern with signature?

    --IDDQ pattern generation and Analysis: This Is Analog!?
    IDDQ analysis. How leakage current estimated. Pull up, pull down in IDDQ pattern generation. Tristate in iddq pattern generation. How to efficiently generate IDDQ pattern. Delta IDDQ. Delta IDDQ in wafer sorting.

    --DFT flows: Yes, That’s Where I Am Now
    a) SOC test: directly test big memory through MBIST, macro test embedded small memory, black box analog module, ATPG, pattern simulation, mismatch debugging, diagnosis.
    b)Full scan.
    c) Multiple identical module testing: pin sharing; xor scanouts (aliasing)
    d) Fault simulating functional pattern, ATPG.
    e) LSSD design flow.
    f) MBIST flow
    g) LBIST flow

    IEEE Testing Standards and EDA Tools: Do They Matter to Me?
    Why each tester has its own hardware language?
    IEEE 1450.1 STIL: the new trend in test language. Structure, waveform definition. (an atpg with boundary scan example)
    IEEE 1450.6 CTL

    Engineering IC Debugging: DFT Engineers Hate It